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The paper presents the model's core of fully depleted SOI MOSFET transistor. The model validated on UTSOI technology including temperature dependence. This model is implemented in VerilogA language, compatible with all commercial circuit simulators. Validation of this compact model performed with Eldo 2010.2, HSPICE 2009.09 and ADS 2006. Introduction of this model into commercial IC simulator in progress.