By Topic

3D-IC floorplanning: Applying meta-optimization to improve performance

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Frantz, F. ; Lyon Inst. of Nanotechnol., Univ. de Lyon, Ecully, France ; Labrak, Lioua ; O'Connor, I.

The introduction of 3D chip architectures is an increasingly attractive integration solution due to the potential performance improvement, power consumption reduction and heterogeneous integration. With another dimension to take into account, the complexity of 3D floorplan algorithms is increased. In this paper we discuss the implementation of such an algorithm and identify parameters that play a role in the solution quality. We then propose the use of a genetic algorithm to discover sets of parameters that guarantee good floorplan quality. The optimized floorplanner rivals existing state of the art tools, proving the efficiency of our method.

Published in:

VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on

Date of Conference:

3-5 Oct. 2011