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3D-IC floorplanning: Applying meta-optimization to improve performance

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3 Author(s)
Frantz, F. ; Lyon Inst. of Nanotechnol., Univ. de Lyon, Ecully, France ; Labrak, Lioua ; O'Connor, I.

The introduction of 3D chip architectures is an increasingly attractive integration solution due to the potential performance improvement, power consumption reduction and heterogeneous integration. With another dimension to take into account, the complexity of 3D floorplan algorithms is increased. In this paper we discuss the implementation of such an algorithm and identify parameters that play a role in the solution quality. We then propose the use of a genetic algorithm to discover sets of parameters that guarantee good floorplan quality. The optimized floorplanner rivals existing state of the art tools, proving the efficiency of our method.

Published in:

VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on

Date of Conference:

3-5 Oct. 2011

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