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Context-aware compiled simulation of out-of-order processor behavior based on atomic traces

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2 Author(s)
Plyaskin, R. ; Inst. for Integrated Syst., Tech. Univ. Munchen, Munich, Germany ; Herkersdorf, A.

Advanced out-of-order processors exhibit complex dynamic behavior. Therefore, they are difficult to model at abstraction levels higher than cycle-accurate instruction set simulators (ISS's). Conventional compiled simulation techniques have been widely used for fast performance estimation. However, they assume static time intervals between memory accesses and do not consider diverse behavior of out-of-order processors. In this paper, we introduce context-aware compiled simulation, in which the timing of basic blocks is defined dynamically, depending on the previously executed basic blocks. We extend binary-level compiled simulation correspondingly and show that consideration of contexts can significantly increase the accuracy of performance estimation. With the proposed technique, we could reduce the average error of timing estimation to 0,47% at average speedup of 45× compared to sim-outorder simulator from the SimpleScalar tool set.

Published in:

VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on

Date of Conference:

3-5 Oct. 2011