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A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme

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3 Author(s)
Ying Fei Teh ; Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong, China ; Zhiliang Qian ; Chi-ying Tsui

With reducing feature size of transistors and increasing number of cores on a single chip, system-on-chips (SoCs) are becoming more vulnerable to faults due to the physical level defects of VLSI fabrication. Fault tolerance and reliability have become two significant challenges for SoC designers. In this work, we propose a novel and efficient scheme to handle the faulty links of a network-on-chip (NoC) by adaptively combining two schemes, namely the link sharing scheme and partial fault link utilization scheme. With our approach, the system is able to optimize the usage of the remaining bandwidth of the links under different fault conditions. Experimental results show a significant improvement in average latency and maximum delay by using the proposed combined scheme with only 4.62% of hardware overhead cost. Our proposed scheme offers a way to increase the effective yield of large and complex NoC systems by enabling the usage of faulty chip with little compromise in the latency performance.

Published in:

VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on

Date of Conference:

3-5 Oct. 2011