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VLSI technological advances provide designers with more and more powerful and flexible platforms such as reconfigurable heterogeneous multiprocessing systems based on FPGAs. At the same time, the applications which are to be implemented onto such platforms are increasingly more and more complex, such as within the field of wireless communications, in particular for software defined radios. Mapping such applications onto such platforms typically results in a very large design space, i.e. a large numbers of candidate implementation solutions. Given the time-to-market pressure faces by many companies, it is generally desirable that designers have access to methods and tools that enable them to explore such large design space rapidly, especially during the initial phases of the design flow so as to prune the design space and then refine the exploration of a reduced number of candidate solutions. In this Work-In-Progress paper we introduce our set of high-level estimation models for Area-Time costs of applications mapped onto FPGA-based multiprocessing reconfigurable architectures. In particular, we suggest models for static and dynamic implementations, taking various internal and external architectural elements into account. We believe that such models could be used for rapidly comparing implementation alternatives at a high level of abstraction and for guiding the designer during the (pre)analysis phase of the design flow for the implementation of e.g. SDR platforms.
Date of Conference: 3-7 Oct. 2011