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CPACT - The conditional parameter adjustment cache tuner for dual-core architectures

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2 Author(s)
Rawlins, M. ; Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA ; Gordon-Ross, A.

Cache tuning reveals substantial energy savings for single-core architectures, but has yet to be explored for multi-core architectures. In this paper we explore level one (L1) data cache tuning in a heterogeneous dual-core system where each data cache can have a different configuration. We show that L1 data cache tuning in a dual-core system achieves 25% average energy savings, which is comparable to single-core data cache tuning. We present the dual-core tuning heuristic CPACT, which finds cache configurations within 1% of the optimal configuration while searching only 1% of the design space. Finally, we provide valuable insights on core-interactions and data coherence revealed when tuning the multithreaded SPLASH-2 benchmarks.

Published in:

Computer Design (ICCD), 2011 IEEE 29th International Conference on

Date of Conference:

9-12 Oct. 2011