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A machine learning approach to modeling power and performance of chip multiprocessors

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5 Author(s)
Changshu Zhang ; Dept. of Electr. & Comput. Eng., Univ. of North Carolina at Charlotte, Charlotte, NC, USA ; Ravindran, A. ; Datta, K. ; Mukherjee, A.
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Exploring the vast microarchitectural design space of chip multiprocessors (CMPs) through the traditional approach of exhaustive simulations is impractical due to the long simulation times and its super-linear increase with core scaling. Kernel based statistical machine learning algorithms can potentially help predict multiple performance metrics with non-linear dependence on the CMP design parameters. In this paper, we describe and evaluate a machine learning framework that uses Kernel Canonical Correlation Analysis (KCCA) to predict the power dissipation and performance of CMPs. Specifically we focus on modeling the microarchitecture of a highly multithreaded CMP targeted towards packet processing. We use a cycle accurate CMP simulator to generate training samples required to build the model. Despite sampling only 0.016% of the design space we observe a median error of 6-10% in the KCCA predicted processor power dissipation and performance.

Published in:

Computer Design (ICCD), 2011 IEEE 29th International Conference on

Date of Conference:

9-12 Oct. 2011

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