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Investigation of reduced models of capacitive loaded interconnects for the high-speed SI applications

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3 Author(s)
Ravelo, B. ; Grad. Sch. of Eng., IRSEEM, ESIGELEC, St. Etienne du Rouvray, France ; Eudes, T. ; Jastrzebski, A.K.

The paper presents a reduced modeling method of a microstrip interconnect for the signal integrity (SI) applications. First- and second- order polynomial models of interconnects based on distributed RLCG model of a transmission line are investigated. Model accuracies are compared with exact circuit/EM co-simulations for a typical high-speed 20 μm-wide microstrip interconnect on Alumina substrate for varying interconnect lengths between 1 and 10 mm and for signal data rates between 1 and 10 Gbit/s. It is shown that the second-order model has a relative amplitude and phase errors lower than 1% from DC to 40 GHz. Also, the second-order model predicts very well the time-domain response to a pulse signal, making it suitable for the accurate prediction of the degradation of RF/digital signals in the high-speed integrated systems.

Published in:

EMC Europe 2011 York

Date of Conference:

26-30 Sept. 2011