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Decreasing the power supply voltage in dynamic voltage frequency scaling to save power consumption may introduce extra delays in CMOS circuits, which may cause errors. This paper presents the probabilistic delay fault model (PDFM), which describes the probability of an error occurring as a function of the power supply voltage and the clock period in synchronous CMOS circuits. In a wide range of applications (graphic, video, digital filtering, etc.), errors occurring with low probability and not remaining for a long time are acceptable. For combinational circuits which have long critical paths with low probability of excitation, a performance increase is achieved with a certain rate of errors determined by the PDFM compared with the traditional design which considers the worst case. The PDFM applied to array multipliers and ripple carry adders shows the agreement of the predicted probabilities with simulated delay histograms to support the practicality of using the PDFM to select power supply voltage and clock period in dynamic voltage frequency scaling circuits with tolerable error rates.