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Image processing algorithm acceleration using reconfigurable macro processor model

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3 Author(s)
Guangfu, Sun ; School of Electronic Science and Engineering, National University of Defense Technology, Changsha 410073, P. R. China ; Huaming, Chen ; Huanzhang, Lu

The concept and advantage of reconfigurable technology is introduced. A kind of processor architecture of reconfigurable macro processor (RMP) model based on FPGA array and DSP is put forward and has been implemented. Two image algorithms are developed: template-based automatic target recognition and zone labeling. One is estimating for motion direction in the infrared image background, another is line picking-up algorithm based on image zone labeling and phase grouping technique. It is a kind of “hardware” function that can be called by the DSP in high-level algorithm. It is also a kind of hardware algorithm of the DSP. The results of experiments show the reconfigurable computing technology based on RMP is an ideal accelerating means to deal with the high-speed image processing tasks. High real time performance is obtained in our two applications on RMP.

Published in:

Systems Engineering and Electronics, Journal of  (Volume:15 ,  Issue: 2 )