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A smart image sensor was developed which integrates a digital pixel image sensor array with an image processor, designed for wireless endoscope capsules. The camera-on-a-chip architecture and its on-chip functionality facilitate the design of the packaging and power consumption of the integrated capsule. The power reduction techniques were carried out at both the architectural and circuit level. Gray coding and power gating in the sensor array to eliminate almost 500/0 of the switch activity on the data bus and more than 99% of the power dissipation in each pixel at a transmitting rate of 2 frames per second. Filtering and compression in the processor reduces the data transmission by more than 2/3. A parallel fully pipelined architecture with a dedicated clock management scheme was implemented in the JPEG-LS engine to reduce the power consumption by 15.7%. The smart sensor has been implemented in 0.18 urn CMOS technology.