By Topic

FIDER: A force-balance-based interconnect delay driven re-synthesis algorithm for data-path optimization after floorplan

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
5 Author(s)
Wang, Yunfeng ; Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China ; Sian, Jinian ; Hong, Xianlong ; Zhou, Qiang
more authors

As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-synthesis after floorplan is expected to be very helpful for reducing the interconnect delay of a circuit. In this paper, a force-balance-based re-synthesis algorithm for interconnect delay optimization after floorplan is proposed. The algorithm optimizes the interconnect delay by changing the operation scheduling and the functional unit allocation and binding. With this method the number and positions of all functional units are not changed, but some operations are allocated or bound to different units. Preliminary experimental results show that the interconnect wire delays are reduced efficiently without destroying the floorplan performance.

Published in:

Tsinghua Science and Technology  (Volume:12 ,  Issue: 1 )