Cart (Loading....) | Create Account
Close category search window
 

Reduction of Parasitic Capacitance Impact in Low-Power SAR ADC

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Chenglong Zhang ; Electr. & Comput. Eng. Dept., Southern Illinois Univ., Carbondale, IL, USA ; Haibo Wang

Many low-power successive approximation register analog-to-digital converters (ADCs) use separate small capacitors, instead of the entire charge scaling (CS) capacitor arrays, to sample the analog inputs. While reducing power consumption, it makes these ADCs prone to gain errors and input range reduction caused by parasitic capacitance of the CS array. This paper presents an effective technique with negligible hardware overhead to address this problem. Simulation results are also presented to validate the proposed technique.

Published in:

Instrumentation and Measurement, IEEE Transactions on  (Volume:61 ,  Issue: 3 )

Date of Publication:

March 2012

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.