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Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming

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3 Author(s)
Tanakamaru, S. ; Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan ; Hung, C. ; Takeuchi, K.

Highly reliable and low power solid-state drive (SSD) is proposed. Through the analysis based on measured error rate in the SSDs with NAND flash memories, the memory cell error shows the asymmetric characteristic in multilevel cell (MLC) NAND flash memories. The proposed asymmetric coding increases the number of “1” s or “0” s of the programming data to reduce the data retention error. The numbers of the memory cells in the higher VTH states are reduced. The memory cell error is reduced by 90% with the asymmetric coding. On the other hand, the inter bit-line capacitance significantly increases with the scaling of memory cells. The bit-line charging current becomes unacceptably large. To decrease the write power consumption, the stripe pattern elimination algorithm (SPEA) is proposed. The SPEA eliminates the column-stripe pattern which consumes the maximum power to charge all of the inter bit-line capacitance in a NAND chip. Theoretical analyses are given for both the asymmetric coding and the SPEA. The asymmetric coding and the SPEA can be used together with the other highly reliable or low power techniques such as intelligent interleaving and adaptive code selection scheme and realizes the high reliability and low power consumption.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 1 )