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A networks-on-chip (NoC) cost-effective design method was given based on the globallyasynchronous locally-synchronous (GALS) interconnect structure. In this method, the synchronous mode was used to transmit data among routers, network interface (NI), and intellectual property (IP) via a synchronous circuit. Compared with traditional methods of implementing GALS, this method greatly reduces the transmission latency and is compatible with existing very large scale integration (VLSI) design tools. The platform designed based on the method can support two kinds of packetizing mechanisms, any topology, several kinds of traffic, and many configurable parameters such as the number of virtual channels, thus the platform is universal. An NoC evaluation methodology is given with a case study showing that the platform and evaluation methodology work well.
Date of Publication: April 2009