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Mapping of irregular IP onto NoC architecture with optimal energy consumption

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3 Author(s)
Li, Guangshun ; College of Computer Science and Technology, Harbin Engineering University, Harbin 150001, China; College of Computer Science and Technology, Qufu Normal University, Rizhao 150001, China ; Wu, Junhua ; Ma, Guangsheng

Network on chip (NoC) architectures have been proposed to resolve complex on-chip communication problems. An NoG-based mapping algorithm is shown in this paper. It can map irregular intellectual properties (IPs) cores onto regular tile 2-D mesh NoC architectures. The basic idea is to decompose a large IP into several dummy IPs or integrate several small IPs into one dummy IP, such that each dummy IP can fit into a single tile. It can also allocate buffer space according to the input/output degree and avoid connection congestion by adapting communication density. Experimental data indicate that using the algorithm proposed in this paper, the communication energy can be reduced about 7%.

Published in:

Tsinghua Science and Technology  (Volume:12 ,  Issue: S1 )