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Design and realization of synchronization circuit for GPS software receiver based on FPGA

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4 Author(s)
Yu, Xiaolei ; Navigation Research Center, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, P. R. China; Faculty of Science and Technology, Deakin University, Geelong VIC 3217, Australia ; Sun, Yongrong ; Liu, Jianye ; Miao, Jianfeng

With research on the carrier phase synchronization and symbol synchronization algorithm of demodulation module, a synchronization circuit system is designed for GPS software receiver based on field programmable gate array (FPGA), and a series of experiment is done on the hardware platform. The result shows the all-digital synchronization and demodulation of GPS intermediate frequency (I F) signal can be realized and applied in embedded real-time GPS software receiver system. It is verified that the decision-directed joint tracking algorithm of carrier phase and symbol timing for received signals from GPS is reasonable. In addition, the loop works steadily and can be used for receiving GPS signals using synchronous demodulation. The synchronization circuit for GPS software receiver designed based on FPGA has the features of low cost, miniaturization, low power and realtime. Surely, it will become one of the development directions for GPS and even GNSS embedded real-time software receiver.

Published in:

Systems Engineering and Electronics, Journal of  (Volume:21 ,  Issue: 1 )