Design and implementation of type-2 fuzzy iterative learning controllers using FPGA chip

This paper studies the design and implementation of discrete-time iterative learning controller for a class of discrete-time nonlinear systems. In the first part of this paper, we investigate how to design the learning gain design in order to improve the learning performance. A fuzzy logic system is utilized to implement the learning gain such that the information of system input output coupling matrix is not required. The learning gain is tuned via the fuzzy logic system based on the learning error at the previous trial. A type-2 fuzzy logic system is used to overcome the uncertainties when designing the fuzzy sets. It is shown in the computer simulation that the learning performance can be further improved when compared with the case by using traditional type-1 fuzzy learning gain. In the second part of this paper, the proposed type-2 fuzzy iterative learning controller is realized by a digital circuit for practical applications. The digital circuit is designed by using VHDL code and implemented in an FPGA chip. We conclude from the comparison between MATLAB simulation and experiment result that the designed circuit is correct and feasible.