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A packet filtering mechanism with a packet delay distribution estimation function for IEEE 1588 time synchronization in a congested network

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3 Author(s)
Murakami, T. ; KDDI R&D Labs. Inc., Fujimino, Japan ; Horiuchi, Y. ; Nishimura, K.

This paper presents a packet filtering mechanism by using packet delay distribution estimation for improving the clock stability of time synchronization with IEEE 1588. We study a packet delay distribution estimation method by using a dedicated probing packet, and discuss the applicability of the estimation method for the clock control mechanism in IEEE 1588 slave nodes. Numerical simulations show that the packet delay distribution estimation method is effective for packet filtering in heavily congested networks.

Published in:

Precision Clock Synchronization for Measurement Control and Communication (ISPCS), 2011 International IEEE Symposium on

Date of Conference:

12-16 Sept. 2011