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A generic execution model for efficient performance evaluation of system architectures at transaction level

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3 Author(s)
Le Nours, S. ; IREENA, Univ. Nantes, Nantes, France ; Barreteau, A. ; Pasquier, O.

Models are necessary to assist system architects in evaluating performances of hardware/software architectures and performing early exploration of the design space. Efficient modeling approaches are then required to cope with the still increasing complexity of embedded systems. In this paper, we present a generic execution model to favor creation of transaction level models for performance evaluation and architecture exploration. Based on this generic model, the created models are used to evaluate by simulation expected processing and memory resources related to system architectures. The benefits of the proposed approach are highlighted through the analysis of an heterogeneous architecture implementing the reception part of the physical layer of the LTE protocol.

Published in:

Specification and Design Languages (FDL), 2011 Forum on

Date of Conference:

13-15 Sept. 2011

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