Assertion support in high-level synthesis design flow

The increasing complexity of System-On-Chip applications increases the challenge of the design task, and specifically the verification process. Assertion-Based Verification is one of the key innovations to simplify RTL verification and facilitate design reuse. However, current design automation tools do not take into account assertions found in behavioral source codes during the High-Level Synthesis (HLS) process. This work focuses on a methodology for automatic detection and transformation of behavioral untimed assertions from a transaction-level description into temporal RTL assertions. This process is introduced as a particular task of a HLS design flow. RTL monitors are generated either in PSL or VHDL language, for simulation purpose. Therefore, this approach contributes to IP-reuse methodologies as input transaction assertions (checking the correctness of data provided by the system) can be exploited in automatically generated IPs.