Skip to Main Content
In harsh environment, circuits that monitor a design must be less sensitive to environmental conditions than the Circuit Under Verification itself. The asynchronous Quasi Delay Insensitive technology provides a good solution to cope with temperature and voltage variations. This approach has been used to design asynchronous ”monitors”, small IP's that are added to the synchronous Circuit Under Verification in order to check some properties. However, the asynchronous monitors are impacted by the synchronous timing assumptions, thus leading to conflicting results.