By Topic

Design and development of FPGA based adaptive thresholder for image processing applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Azeema Sultana ; VLSI Design & Embedded System, Dr. Ambedkar Institute of Technology, Bangalore, India ; M. Meenakshi

This paper presents design, implementation and real time validation of Image binarization process using weight based clustering algorithm, which uses the clustering property of neural network. The generic technique for image binarization requires choosing a threshold value and comparing the pixel values with the threshold and classifying as black and white. The proposed algorithm calculates a global optimum threshold by learning from the image background and foreground features. A simple two-weight neural network is implemented to cluster the foreground and background pixels. Here an adaptive thresholding technique based on competitive learning is selected for Weight Updating. The developed algorithm is implemented on a FPGA platform hardware system, which consists of two functional blocks. The first block is used to obtain the threshold value for the image frame; another block to apply the threshold value to the frame. This parallelism and the simple hardware component of both blocks make this approach suitable for real-time applications, while the performance remains comparable with the Otsu technique frequently used in off-line threshold determination. Results from the proposed algorithm are presented for numerous examples, both from simulations and experimentally using the FPGA.

Published in:

Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE

Date of Conference:

22-24 Sept. 2011