Cart (Loading....) | Create Account
Close category search window
 

A case study of process-variation effect to SoC analog circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Latif, M.A.A. ; Electr. & Electron. Eng., Univ. Teknol. Petronas, Tronoh, Malaysia ; Ali, N.B.Z. ; Hussin, F.A.

Recent submicron process technology scaling leads the urgency to build an efficient methodology of characterizing and modeling the process variation effect, for example, the threshold voltage, Vt. This is one of the key process parameters that must be extensively modeled and validated for accurate circuit performance. Furthermore, this requirement is even much more critical for analog applications which demand an ability to match devices precisely. Analog circuits use larger device dimensions as compared to digital circuits in order to minimize the process variation implication. This has led Negative Bias Temperature Instability (NBTI) to be the most performance limiter compared to the rest of reliability mechanisms. This reliability sensitivity is even more challenging as most of the circuit blocks (digital and analog) are fabricated on the same chip for system-on-chip (SoC) applications. This paper will describe in detail the actions taken to minimize impact to customers and will show how important proper aging simulations to be conducted with the right combination of process, voltage, temperature (PVT) and coupling/timing to occur due to process variation effect beyond specifications on analog differential amplifier (diffamp) circuits in SoC products.

Published in:

Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE

Date of Conference:

22-24 Sept. 2011

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.