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The present scenario of spectacular fusion of chip size reduction and increase in number of circuits on chips has given a tremendous growth in battery operated and power sensitive applications thus leading to the growth in the emerging field of Low Power Electronics. In our paper we are indulged in Static Power reduction at the Architectural level as in near future this area of power is going to rule the total amount of dissipated power in the SOCs (System On Chip).We have proposed of synthesizing the POWER GATING TECHNIQUE in specific the Fine grained method in order to optimize the static power being dissipated. In this approach the inputs to the gates are blocked by using NMOS when not in use thus resulting in reduction of unnecessary utilization of input leading to significant amount of power reduction. Thus our whole paper revolves around the concept of reduction of static power at Architectural level starting with 1 bit and extending till 8 bit with corresponding decrease in the power consumption. The simulation is done using MODELSIM and MICROWIND software.