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An efficient video decoder design for MPEG-2 MP@ML

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2 Author(s)
Jui-Hua Li ; Dept. of Comput. Eng., Santa Clara Univ., CA, USA ; Nam Ling

In this paper, we present an efficient MPEG-2 video decoder architecture design to meet MP@ML real-time decoding requirement. The overall architecture, as well as the design of the major function-specific processing blocks, such as the variable-length decoder, the inverse 2-D discrete cosine transform unit, and the motion compensation unit, are discussed. A hierarchical and distributed controller approach is used and a bus-monitoring model for different bus arbitration schemes to control external DRAM accesses is developed and the system is simulated. Practical issues and buffer sizes are addressed. With a 27 MHz clock, our architecture uses much fewer than the 667 cycles, upper bond for the MP@ML decoding requirement, to decode each macroblock with a single external bus and DRAM

Published in:

Application-Specific Systems, Architectures and Processors, 1997. Proceedings., IEEE International Conference on

Date of Conference:

14-16 Jul 1997

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