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Realization of a nonlinear digital filter on a DSP array processor

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3 Author(s)
H. Kwan ; Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA ; E. J. Powers ; E. E. Swartzlander

This paper presents the performance evaluation of a fast third-order Volterra digital filtering algorithm mapped onto an AT&T DSP-3 parallel processor. Five different implementations are considered. Speed-up results indicate that the “time-skewing” method is currently the fastest. An application to nonlinear communication channel equalization using a 64-QAM signal constellation is presented

Published in:

Application-Specific Systems, Architectures and Processors, 1997. Proceedings., IEEE International Conference on

Date of Conference:

14-16 Jul 1997