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A congestion-driven placement improvement algorithm for large scale sea-of-gates arrays

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5 Author(s)
T. Sadakane ; Mitsubishi Electr. Corp., Itami, Japan ; H. Shirota ; K. Takahashi ; M. Terai
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A fast placement improvement algorithm for large scale gate arrays is reported. This algorithm consists of a new cell padding phase and a fast iterative improvement phase. To reduce local routing congestion on a chip, the padding phase virtually expands the size of cells in the congested regions and relocates all the cells to eliminate the cell overlap, preserving the relative cell position. We have developed a formula by which to estimate from the expanded cell sizes the congestion after the relocation in each region on a chip. Using this, the padding phase determines cell sizes that will equalize the congestion throughout a chip, by simulated annealing. The iterative improvement phase minimizes the well known objective function that takes the local congestion into account, but our algorithm is faster because of the use of a new gain estimation method for determining a better position to which to move a cell. The experimental results on large gate array designs indicate that the routability of cell placement is considerably improved by our algorithm

Published in:

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Date of Conference:

5-8 May 1997