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TSV (Through Silicon Via) has been widely welcomed as an enabling technology for three-dimensional integration in a package with high density. The developing of a drilling method for TSVs with tapered sections by experimental methodology can be a tedious task. This paper reports on a advanced deep reactive ion etch process technology for the tapering of deep silicon vias which can be used in the fabrication of through silicon interconnection for 3D system in packaging application. The process consists of two etching steps: the 1st BOSCH etching step is designed to etch vertical 150-200um deep through-silicon vias. And the 2nd etch step is designed to control the taper angle of the via. These features (30-80 μm in diameter) are aimed for applications in 3D integration and MEMS packaging. The effects of various time of 2nd etch step on the via profile development are investigated. lt has been demonstrated that it is feasible to achieve a controllable via taper to realize a void-free copper via-filling by electroplating process.