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Improving the performance of an SOC design for network processing based on FPGA with PlanAhead

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5 Author(s)
Kang Li ; Dept. Microelectronics Xidian University, Xi'an, China ; Li Lei ; Qing Guang ; Jiang-Yi Shi
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The study in this paper is aimed at improving the performance of a network processor design (XDNP) based on a Virtex-4 FPGA by using the PlanAhead tool offered by XILINX. PlanAhead gives a unique visibility into the design. The tool can very quickly identify the critical path, and then supply hierarchical floorplanning to achieve faster timing closure. XDNP is targeted at networking applications requiring a high degree of flexibility, programmability, scalability and performance[3]. During this work Some design partitions, which are referred as physical blocks (Pblocks) are created to constrain critical circuitry within areas. By applying floorplanning techniques with PlanAhead, the system performance is optimized by 14%, while the run time decreases by 27.6% on the average.

Published in:

Electronics, Communications and Control (ICECC), 2011 International Conference on

Date of Conference:

9-11 Sept. 2011