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3780 point FFT is generally implemented by decomposing 3780 point to small size, which can be implemented with WFTA and PFA. Pipelined architecture is most commonly used when implementing 3780 FFT in ASIC. Several architectures were proposed and patented, the differences of the architectures lie in the way 3780 are decomposed and the processing order of small sized WFTA module. In this paper, the architectures for 3780 point FFT processor are analyzed, and the architectures with varied processing order and internal wordlength are modeled and simulated with Matlab, the simulation results show that processing larger sized WFTA at the first stages can achieve better performance, and the decomposition of 3780 = 9 × 3 × 7 × 5 × 4 can achieve best performance in terms of SQNR and hardware cost.