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A low power 170 MHz discrete-time analog FIR filter

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2 Author(s)
Wang, X. ; California Univ., Davis, CA, USA ; Spencer, R.R.

A 170 MHz analog FIR filter operating from a single 3.3 V supply is described. The design has been fabricated in the HP 1.2 μm CMOS process and has an area of 2.35 mm by 1.97 mm including bonding pads. This 9-tap filter dissipates 70 mW when operating at 170 MHz. The multipliers are implemented using MDAC's with 6-bit resolution

Published in:

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Date of Conference:

5-8 May 1997

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