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A High-Performance and Energy-Efficient Virtually Tagged Stack Cache Architecture for Multi-core Environments

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4 Author(s)

Virtually tagged caches possess a key attribute that renders them more attractive than Physically Indexed, Physically Tagged (PIPT) caches, they operate natively within the virtual address space, hence taking full advantage of the original intention of a virtual memory implementation: the illusion of a contiguous address space. Consequently, virtually tagged caches eliminate Translation Look-aside Buffer (TLB) references, yielding both energy and performance improvements. On the other hand, virtually tagged caches incur substantial overhead in resolving homonym/synonym issues, which is a fairly complicated process in contemporary multicore environments. In this paper, we aim to markedly alleviate this overhead through the use of a new virtually tagged stack cache design specifically targeting multi-core environments. It will be demonstrated that special level-one virtually tagged stack caches can significantly boost the performance of a system running a heavy, dominating, multi-threaded workload -- among other applications -- while actually reducing its energy consumption. This scheme is aimed at modern server environments that run a single, dedicated multi-threaded application workload per server. The proposed virtually tagged stack cache for multi-core processors minimizes the overhead incurred in resolving virtual-tag-related artifacts, by granting exclusive access to only one multi-threaded workload at a time. In other words, said virtually tagged cache filters the Virtual Address (VA) spaces and subsequently handles only the stack areas of the selected virtual address space. A cost effective way to implement the proposed stack cache for multi-core systems is also presented, yielding average performance improvements of around 20%.

Published in:

High Performance Computing and Communications (HPCC), 2011 IEEE 13th International Conference on

Date of Conference:

2-4 Sept. 2011

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