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A 65 nm CMOS 4-Element Sub-34 mW/Element 60 GHz Phased-Array Transceiver

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7 Author(s)
Tabesh, M. ; Univ. of California, Berkeley, Berkeley, CA, USA ; Jiashu Chen ; Marcu, C. ; Lingkai Kong
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This paper describes a low power and element-scalable 60 GHz 4-element phased array transceiver implemented in a standard 65 nm CMOS process. Using a 1.2 V supply, the array consumes <;34 mW/element including LO synthesis and distribution. Energy and area efficiency are achieved by utilizing a baseband phase shifting architecture, holistic impedance optimization, and lumped-element based design. Each receiver (RX) element provides 24 dB of gain with an average noise figure (NF) of 6.8 dB while the total saturated output power of the transmitter (TX) is 4.5 dBm. The array achieves 360° of phase shifting range with a worst-case measured phase resolution of 6 bits (TX)/ 5 bits (RX) while maintaining amplitude variations less than ±0.5 dB.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:46 ,  Issue: 12 )

Date of Publication:

Dec. 2011

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