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Abstract-A vector sum phase shifter (VSPS) using 90 nm CMOS process is presented. The VSPS can synthesize any amplitude and phase at certain frequencies, so the phase and amplitude error can be minimized. The proposed VSPS using a wideband Wilkinson power divider with left-hand transmission line (LHTL)/right-hand transmission line (RHTL) elements to achieve low phase error over a wide bandwidth. The measured RMS phase and amplitude error are under 5.1° and 0.5 dB over 57-66 GHz, respectively. The average amplitude is about -5 dB. The dc power consumption is less than 15.6 mW (13 mA, 1.2 V). The chip area is 0.315 mm2 without pads. To the authors knowledge, this phase shifter demonstrates the lowest RMS phase and amplitude error over a wide bandwidth among the reported phase shifters around 60 GHz in CMOS processes.