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Investigation of Tunneling Current in \hbox {SiO}_{2}/ \hbox {HfO}_{2} Gate Stacks for Flash Memory Applications

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10 Author(s)
Chakrabarti, B. ; Univ. of Texas at Dallas, Richardson, TX, USA ; Heesoo Kang ; Brennan, B. ; Tae Joo Park
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Despite theoretical predictions of significant performance improvement in Flash memory devices using tunnel-barrier-engineered (TBE) structures, there have been very few reports that demonstrate experimental verification. In this work, we have studied the role of factors such as high-k layer thickness and annealing recipe on the performance of SiO2/HfO2 gate stacks by electrical and physical characterization techniques. Results indicate that thick HfO2 is not suitable for use in SiO2/HfO2 stacks for tunnel barrier engineering applications. The performance of SiO2/HfO2 stacks improves with decreasing thickness of the HfO2 layer. Mild (10%) O2/N2 anneals do not significantly affect performance, although annealing above 600°C resulted in a slight decrease in the program current. Based on our observations, we propose a method to improve the program current in these structures and a simple hypothesis for the physical model for tunneling in SiO2/HfO2 stacks.

Published in:

Electron Devices, IEEE Transactions on  (Volume:58 ,  Issue: 12 )

Date of Publication:

Dec. 2011

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