By Topic

Chip scale packaging using chip-on-flex technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
R. Fillion ; Gen. Electr. Corp. Res. & Dev. Center, Schenectady, NY, USA ; B. Burdick ; D. Shaddock ; P. Piacente

An increasing number of electronic designers, fabricators and users see Chip Scale Packaging (CSP) as a way to obtain the benefits foreseen in multichip packaging and Chip-on-Board (COB) without the problems and limitations currently associated with each. The Chip-on-Flex (COF) multichip packaging technology has been demonstrated to be applicable to single chip packages that meet chip scale packaging goals. This paper looks at the Chip-on-Flex Chip Scale technology and addresses issues including the process, structure, assembly, yields and reliability

Published in:

Electronic Components and Technology Conference, 1997. Proceedings., 47th

Date of Conference:

18-21 May 1997