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Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy

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7 Author(s)
Shunsuke Okumura ; Kobe University, Japan, 2JST, CREST, Japan ; Yohei Nakata ; Koji Yanagida ; Yuki Kagiyama
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This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-kb blocks in which 8-kb data can be compared in 130.0ns. The proposed scheme reduces power consumption in data comparison by 92.3%, compared to that of a parallel cyclic redundancy check (CRC) circuit.

Published in:

2011 IEEE Custom Integrated Circuits Conference (CICC)

Date of Conference:

19-21 Sept. 2011