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A testchip of 8Gb/s forwarded clock serial link receivers is presented. The receiver exploits a novel low-power super-harmonic injection-locked ring oscillator for symmetric multi-phase local clock generation and dekewing. Further power reduction is achieved by designing most the receiver circuits in the near-threshold region of 0.6V supply, with the exception of only the global clock buffer, test buffers and synthesized digital circuits at nominal 1V supply. At architectural level, 1:10 direct demultiplexing rate is chosen as a demonstration of achieving low supply operation by high-parallelism design. Fabricated in 65nm CMOS technology, two receiver prototypes are integrated in this testchip, one without and the other with front S/Hs. Including the amortized power of global clock distribution, they consume 1.3mW and 2mW respectively at 8Gb/s input data rate, which achieve the power efficiency of 0.163mW/Gb/s and 0.25mW/Gb/s. Measurement results show both receivers get BER <; 10-12 across a 20-cm FR4 PCB channel.