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Test challenges for 3D integration (an invited paper for CICC 2011)

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1 Author(s)
W. R. Bottoms ; 3MTS, Inc., 3003 Bunker Hill Lane, Santa Clara, CA 95054, USA

The impact of increased transistor count, higher frequency, and greater complexity presents many difficult challenges for test. The current trend toward 3D IC integration, driven in part by the need to increase circuit density as Moore's Law scaling slows, makes testing even more difficult. The use of the third dimension, the incorporation of new structures such as Through Silicon Vias (TSV) and new processes developed for thinning and bonding layers for stacked 3D structures all present new challenges for test technology. Test cost may be the most difficult of these many challenges. The solutions to meet these challenges must begin at design with the incorporation of on-chip and on-package design for test (DFT) and built in self test (BIST) infrastructure. The difficult challenges and potential solutions for test are discussed.

Published in:

2011 IEEE Custom Integrated Circuits Conference (CICC)

Date of Conference:

19-21 Sept. 2011