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A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS

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5 Author(s)
I-Ning Ku ; Department of Electrical Engineering, University of California, Los Angeles, 90095, USA ; Zhiwei Xu ; Yen-Cheng Kuan ; Yen-Hsiang Wang
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A 7-bit, 2.2-GS/s time-interleaved subranging CMOS ADC for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A novel time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate mismatches within channels. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm2 chip area and consumes 40 mW at 2.2 GS/s from a 1 V supply. Measured SNDR and SFDR are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate.

Published in:

2011 IEEE Custom Integrated Circuits Conference (CICC)

Date of Conference:

19-21 Sept. 2011