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Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs

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5 Author(s)
Kotabe, A. ; Central Res. Lab., Hitachi, Ltd., Tokyo, Japan ; Kiyoo Itoh, B.S. ; Takemura, R. ; Tsuchiya, Ryuta
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The feasibility of 0.5-V memory-rich nanoscale CMOS LSIs was studied. First, repair techniques and nanoscale FD-SOI MOSTs are discussed in terms of Vt-variation. Second, sub-0.5-V dual-VDD dual-Vt logic circuits are proposed and evaluated by simulation with a 25-nm planar FD-SOI MOST, followed by an investigation of a 0.5-V 1-Gb SRAM/DRAM. Third, the importance of using compensation circuits for process, voltage, and temperature variations is stressed. Finally, it is concluded that a 0.5-V memory-rich CMOS LSI is possible while reducing the power to one-tenth that of a conventional 1-V CMOS LSI if the above devices and circuits are used and the within-wafer Vt-variation is compensated for.

Published in:

Custom Integrated Circuits Conference (CICC), 2011 IEEE

Date of Conference:

19-21 Sept. 2011

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