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Tri-state digital phase-frequency detectors (PFDs) are widely used for the large capture and locking range that they enable, but suffer from relatively large in-band phase noise. Sub-sampling phase detectors have recently been demonstrated to offer very low in-band noise but with only a very small capture range. We show how a PFD and a sub-sampling phase detector can be combined to maintain the phase-frequency detection capabilities while simultaneously obtaining in-band noise suppression. A 2.2GHz PLL is demonstrated in a 65 nm CMOS process with an on-chip loop filter area of 0.04 mm2. The measured in-band phase noise improves from -110 dBc/Hz to -122 dBc/Hz when the auxiliary sub-sampling phase detector is active.
Custom Integrated Circuits Conference (CICC), 2011 IEEE
Date of Conference: 19-21 Sept. 2011