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A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor is implemented in 90nm CMOS technology. A reconfigurable hardware architecture with heterogeneous stream processing and subword-level parallelism is implemented to accelerate the vision processing for smart-camera applications. The area efficiency reaches 111.329 GOPS/mm2. The power efficiency and area efficiency are 4.5× to 33.0× and 3.8× to 74.2× better than the state-of-the-art works, respectively.
Custom Integrated Circuits Conference (CICC), 2011 IEEE
Date of Conference: 19-21 Sept. 2011