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Parallel CRC generation

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2 Author(s)
Albertengo, G. ; Electron. Dept., Politecnico di Torino, Italy ; Sisto, R.

Theoretical aspects of encoding cyclic redundant codes (CRCs) are reviewed. A method of designing hardware parallel encoders for CRCs that is based on digital system theory and z-transforms is presented. It allows designers to derive the logic equations of the parallel encoder circuit for any generator polynomial. A few interesting application areas for hardware parallel encoders are pointed out.<>

Published in:

Micro, IEEE  (Volume:10 ,  Issue: 5 )

Date of Publication:

Oct. 1990

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