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Hardware implementation of a systolic antenna array signal processor based on CORDIC arithmetic

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4 Author(s)
B. Haller ; Dept. of Electr. Eng., Eidgenossische Tech. Hochschule, Zurich, Switzerland ; M. Streiff ; U. Fleisch ; R. Zimmermann

We present the practical hardware implementation of a systolic array for performing recursive least-squares minimisation via orthogonal matrix triangularisation. This is an extremely demanding task for high speed, real-time operation such as required in many modern adaptive antenna, radar, and sonar systems. Since the underlying Givens rotations can be efficiently computed by the CORDIC algorithm, we have implemented a dedicated CORDIC processor element (CPE) in an ASIC. All the required calculations are carried out by a network of these small and simple circuits, which are suitable for constructing a high performance systolic array, either based on MCM technology or as a macro-cell building block for a very highly integrated single chip solution. The design of an adaptive antenna signal processor is described in a top-down manner, from the proposed algorithm down to the bit-level details of the realised component

Published in:

Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE International Conference on  (Volume:5 )

Date of Conference:

21-24 Apr 1997