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This paper proposes novel design methodologies for generating feed forward and recursive architectures for optimal mapping on Field Programmable Gate Arrays (FPGAs). The new methodology keeps in perspective the architecture of FPGA, structural design of logic blocks, their interconnectivity and available special purpose embedded blocks during filter transformation. Higher throughput is achieved through selective application of different transformations, taking into consideration limited pipelining options of these embedded blocks and general construction of FPGA slice fabric. The paper demonstrates the methodology and shows its applicability by synthesizing the designs and comparing the results that show improved performance as compared to traditional designs.