By Topic

An algorithmic transformation for FPGA implementation of high throughput filters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Kamboh, H.M. ; Electr. & Comput. Eng. Dept., Centre of Adv. Studies in Eng., Islamabad, Pakistan ; Khan, S.A.

This paper proposes novel design methodologies for generating feed forward and recursive architectures for optimal mapping on Field Programmable Gate Arrays (FPGAs). The new methodology keeps in perspective the architecture of FPGA, structural design of logic blocks, their interconnectivity and available special purpose embedded blocks during filter transformation. Higher throughput is achieved through selective application of different transformations, taking into consideration limited pipelining options of these embedded blocks and general construction of FPGA slice fabric. The paper demonstrates the methodology and shows its applicability by synthesizing the designs and comparing the results that show improved performance as compared to traditional designs.

Published in:

Emerging Technologies (ICET), 2011 7th International Conference on

Date of Conference:

5-6 Sept. 2011