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Active clamp implementation in complementary BiCMOS process with high voltage BJT devices

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2 Author(s)
Vashchenko, V. ; Nat. Semicond. Corp., Sunnyvale, CA, USA ; Shibkov, A.

A small footprint active clamp design with low voltage CMOS and high voltage BJT components in complementary BiCMOS process is proposed, analyzed by mixed-mode simulation and experimentally validated. The new clamp is composed from stacked NMOS driver and power BJT to achieve appropriate voltage tolerance. Both NPN and PNP-based versions of the clamp are compared to the stacked NMOS clamp.

Published in:

Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2011 33rd

Date of Conference:

11-16 Sept. 2011