By Topic

Active clamp implementation in complementary BiCMOS process with high voltage BJT devices

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Vashchenko, V. ; Nat. Semicond. Corp., Sunnyvale, CA, USA ; Shibkov, A.

A small footprint active clamp design with low voltage CMOS and high voltage BJT components in complementary BiCMOS process is proposed, analyzed by mixed-mode simulation and experimentally validated. The new clamp is composed from stacked NMOS driver and power BJT to achieve appropriate voltage tolerance. Both NPN and PNP-based versions of the clamp are compared to the stacked NMOS clamp.

Published in:

Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2011 33rd

Date of Conference:

11-16 Sept. 2011