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The pressure-assisted sintering of a sub-micrometer silver paste-sometimes called “silver-sintering” or “low temperature joining technique (LTJT)”-is already used in many power electronics industry applications and provides die-attach layers with excellent mechanical, electrical, and thermal properties. The present challenge is to fit both the coefficient of thermal expansion (CTE) and the mechanical properties of the die-attach layer to the characteristics of chip and substrate to reduce the thermal stress occurring in the attach layer during temperature cycling. After evaluating the impact of the CTE of the sintered die-attach layer on the thermomechanical stress in a whole chip-to-substrate system, we demonstrate that adding special filling materials like SiC or h-BN particles to the silver-powder leads to a significant reduction of the CTE. Further measurements show that thereby the mechanical stability and the electrical conductivity are reduced in an acceptable range. In order to provide a tool for predicting the influence of additives on the LTJT layers' elasticity and thermal expansion, these properties are modeled based on the amount and type of the additive. Finally, the resulting stress reduction caused by implementation of the modified sinter-layers is estimated by employing finite elements method simulation.